Nanoscale CMOS technologies are posing new challenges to IC designers. Interconnects are becoming the main design limitation and having a deep influence not only to electrical design of circuits but to also constraining the architectural design choices. Furthermore, to manage the electrical design at system level is very challenging unless a well defined design guidelines are established. In this presentation I will review some of the key challenges in electrical design from traditional circuit perspective in nanoscale CMOS. Furthermore, in order to mitigate the impact of interconects, I will also discuss on some new emerging architectural styles like Network-on-Chip. For NoC related structures I will review what new design challenges and issues we are facing when we encapsulate and abstract away the traditional electrical issues, as discussed in the first part of my talk.